ZSSC3218 Datasheet, PDF (34/55 Pages) Integrated Device Technology – High-End 18-Bit Sensor Signal Conditioner

ZSSC3218 Datasheet
MTP
Address
Word / Bit
Range
Default
Setting
Description
11:10
00BIN
CKP_CKE
14:12
000BIN
CYC_period
15
0BIN
SOT_curve
Notes / Explanations
Clock polarity and clock-edge select—determines
polarity and phase of SPI interface clock with the
following modes:
00  SCLK is low in idle state, data latch with
rising edge and data output with falling
edge
01  SCLK is low in idle state, data latch with
falling edge and data output with rising
edge
10  SCLK is high in idle state, data latch with
falling edge and data output with rising
edge
11  SCLK is high in idle state, data latch with
rising edge and data output with falling
edge
Update period (ZSSC3218 sleep time, except
oscillator) in cyclic operation:
000  not assigned
001  125ms
010  250ms
011  500ms
100  1000ms
101  2000ms
110  4000ms
111  not assigned
Type/shape of second-order curve correction for the
sensor signal.
0  parabolic curve
1  s-shaped curve
© 2016 Integrated Device Technology, Inc.
34
April 20, 2016