5L35021 Datasheet, PDF (34/37 Pages) Integrated Device Technology – Clock Generator

5L35021 Datasheet
Byte 35: DIFF2 Control Register
Byte 23h
Name
Control Function
Type
0
1
PWD
Bit 7
DIFF2_CLK_SEL
Differential clock 2 source selection R/W
DIV1
Bit 6
Reserved
DIV3
0
1
Bit 5 DIFF2_OUTPUT_TYPE[1] Differential clock 2 type select bit 1 R/W
00: LVMOS 01: Reserved
1
Bit 4 DIFF2_OUTPUT_TYPE[0] Differential clock 2 type select bit 0 R/W
10: Reserved 11: LPHCSL
1
Bit 3
Reserved
0
Bit 2
Reserved
1
Bit 1
DIFF2_CMOS_SLEW
Differential clock 2 LVCMOS slew
rate control
R/W
normal
Bit 0
DIFF2_CMOS2_EN
Differential clock 2 LVCMOS
output_B control
R/W
disable
strong
0
enable
0
Byte 36: SE1 and DIV4 control
Byte 24h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
I2C_PDB
Ref_free_run
SE1_Freerun_32K
SE1_CLKSEL1
REF_EN
DIV4_CH3_EN
DIV4_CH2_EN
Control Function
Type
0
chip power down control bit
Reference clock output
R/W power down
R/W
stop
Reserved
SE1 clock output default
SEL1 output select
REF output enable
R/W 32k freerun
R/W
DIV5
R/W
disable
DIV4 channel 3 output control R/W
DIV4 channel 3 output control R/W
disable
disable
1
PWD
normal
1
freerun
0
0
B36bit3 control 0
DIV4
1
enable
1
enable
0
enable
0
©2017 Integrated Device Technology, Inc.
34
July 13, 2017