5L35021 Datasheet, PDF (3/37 Pages) Integrated Device Technology – Clock Generator

5L35021 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
Name
Type
14
DIFF1B
Output
15
DIFF1
Output
16
V_SSDIFF1
Power
17
V_DDDIFF2
Power
18
DIFF2B
Output
19
DIFF2
Output
20
V_SSDIFF2
Power
EPAD
Power
Description
Differential clock output 1_Complement; can be OTP pre-programmed to
LVCMOS/LPHCSL output type.
Differential clock output 1_True; can be OTP pre-programmed to LVCMOS/LPHCSL
output type.
Connect to ground.
Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF2.
Differential clock output 2_Complement; can be OTP pre-programmed to
LVCMOS/LPHCSL output type.
Differential clock output 2_True; can be OTP pre-programmed to LVCMOS/LPHCSL
output type.
Connect to ground.
Connect to ground pad.
Detailed Block Diagram
CLKINB/X1
CLKIN/X2
VBAT
VDD18
VDDA
VSS
SCL_DFC 1
SDA_DFC0
OSC
PLL1
MUX
DIV
1
DIV
2
DIV1 /REF
DIV3
MUX
DIV1 /REF
DIV3
MUX
Power
Monitor
POR
Calibration
32.768K
DCO
MUX
PLL2
MUX
PLL3
MUX
DIV
3
MUX
DIV
4
DIV
5
DIV4 /REF
DIV5
32K
MUX
I²C Engine
Overshot Reduction
(ORT)
Dynamic Frequency Control Logic (DFC)
OTP memory (1 configuration)
Proactive Power Saving Logic (PPS)
Timer
VDDDIFF2
DIFF2
DIFF2B
VDDDIFF1
DIFF1
DIFF1B
OE1
SE1
VDDSE1
©2017 Integrated Device Technology, Inc.
3
July 13, 2017