5L35021 Datasheet, PDF (14/37 Pages) Integrated Device Technology – Clock Generator

5L35021 Datasheet
DFC Function Programming
▪ Register B63b3:2 selects DFC00–DFC11 configuration.
▪ Byte16–19 are the registers for PLL2 VCO setting, based on B63b3:2 configuration selection, the data write to B16–19 will be stored
in selected configuration OTP memory.
▪ Refer to DFC Function Priority table. Select proper control pin(s) to activate DFC function.
▪ Note the DFC function can also be controlled by I²C access.
PPS – Proactive Power Saving Function
PPS (Proactive Power Saving) is an IDT patented unique design for the clock generator that proactively detects end device power down
state and then switches output clocks between normal operation clock frequency and low power mode 32kHz clock that only consumes
<2μA current. The system could save power when the device goes into power down or sleep mode. The PPS function diagram is shown
as below.
Figure 3. PPS Function Block Diagram
I²C
&
Logic
Xtal
Oscillator
PPS
Control
Logic
Low
Power
DCO
PLL
XOUT
XIN
MHz / kHz
Switching
Figure 4. PPS Assertion/Deassertion Timing Chart
3rd cycle
2nd cycle
1st cycle
PPS assertion
Xtal
Oscillator
Power
Down
Control
Logic
MHz clock
2nd cycle
1st cycle
PPS deassertion
32k clocks
PPS setting (1-2-4-8)
32k clocks
©2017 Integrated Device Technology, Inc.
MHz clock
14
July 13, 2017