8T49N282 Datasheet, PDF (33/78 Pages) Integrated Device Technology – Auto and manual input clock selection with hitless switching

8T49N282 DATA SHEET
Bit Field Name
GPO6SEL[2:0]
GPO7SEL[2:0]
GPO[7:0]
Rsvd
Field Type
R/W
R/W
R/W
R/W
GPIO Control Register Block Field Descriptions
Default Value Description
000b
Function of GPIO[6] pin when set to output mode by GPIO_DIR[6] register bit:
000 = General Purpose Output (value in GPO[6] register bit driven on GPIO[6] pin
001 = Loss-of-Signal Status Flag for Input Reference 2 reflected on GPIO[6] pin
010 through 111 = reserved
000b
Function of GPIO[7] pin when set to output mode by GPIO_DIR[7] register bit:
000 = General Purpose Output (value in GPO[7] register bit driven on GPIO[7] pin
001 = Loss-of-Signal Status Flag for Input Reference 3 reflected on GPIO[7] pin
010 through 111 = reserved
00h
Output Values reflect on pin GPIO[7:0] when General-Purpose Output Mode selected.
-
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 7J. Output Driver Control Register Bit Field Locations and Descriptions
Output Driver Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
0077
OUTEN[7:0]
0078
POL_Q[7:0]
0079
OUTMODE7[2:0]
SE_MODE7
OUTMODE6[2:0]
007A
OUTMODE5[2:0]
SE_MODE5
OUTMODE4[2:0]
007B
OUTMODE3[2:0]
SE_MODE3
OUTMODE2[2:0]
007C
OUTMODE1[2:0]
SE_MODE1
OUTMODE0[2:0]
D0
SE_MODE6
SE_MODE4
SE_MODE2
SE_MODE0
Bit Field Name Field Type
OUTEN[7:0]
R/W
POL_Q[7:0]
R/W
OUTMODEm
[2:0]
R/W
SE_MODEm
R/W
Output Driver Control Register Block Field Descriptions
Default Value Description
Output Enable control for Clock Outputs Q[7:0], nQ[7:0]:
00h
0 = Qn is in a high-impedance state
1 = Qn is enabled as indicated in appropriate OUTMODEn[2:0] register field
Polarity of Clock Outputs Q[7:0], nQ[7:0]:
00h
0 = normal polarity
1 = inverted polarity
001b
Output Driver Mode of Operation for Clock Output Pair Qm, nQm:
000 = High-impedance
001 = LVPECL
010 = LVDS
011 = LVCMOS
100 = reserved
101 - 111 = reserved
Behavior of Output Pair Qm, nQm when LVCMOS operation is selected
0b
(Must be 0 if LVDS or LVPECL output style is selected):
0 = Qm and nQm are both the same frequency but inverted in phase
1 = Qm and nQm are both the same frequency and phase
REVISION E 07/08/15
33
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