8T49N282 Datasheet, PDF (28/78 Pages) Integrated Device Technology – Auto and manual input clock selection with hitless switching

8T49N282 DATA SHEET
Bit Field Name
M1_1_0[23:0]
M1_1_1[23:0]
M1_1_2[23:0]
M1_1_3[23:0]
LCKBW1[3:0]
ACQBW1[3:0]
LCKDAMP1[2:0]
ACQDAMP1[2:0]
Digital PLL1 Feedback Configuration Register Block Field Descriptions
Field Type Default Value Description
R/W
070000h M1 Feedback divider ratio for Input Reference 0 when used by Digital PLL1.
R/W
070000h M1 Feedback divider ratio for Input Reference 1 when used by Digital PLL1.
R/W
070000h M1 Feedback divider ratio for Input Reference 2 when used by Digital PLL1.
R/W
070000h M1 Feedback divider ratio for Input Reference 3 when used by Digital PLL1.
Digital PLL1 Loop Bandwidth while locked:
0000 = 512mHz
0001 = 1Hz
0010 = 2Hz
0011 = 4Hz
0100 = 8Hz
R/W
0111b
0101 = 16Hz
0110 = 32Hz
0111 = 64Hz
1000 = 128Hz
1001 = 256Hz
1010 = 512Hz
1011 = Reserved
1100 through 1111 = Reserved
Digital PLL1 Loop Bandwidth while in acquisition (not-locked):
0000 = 512mHz
0001 = 1Hz
0010 = 2Hz
0011 = 4Hz
0100 = 8Hz
R/W
0111b
0101 = 16Hz
0110 = 32Hz
0111 = 64Hz
1000 = 128Hz
1001 = 256Hz
1010 = 512Hz
1011 = Reserved
1100 through 1111 = Reserved
Damping factor for Digital PLL1 while locked:
000 = Reserved
001 = 1
010 = 2
R/W
011b
011 = 5
100 = 10
101 = 20
110 = Reserved
111 = Reserved
Damping factor for Digital PLL1 while in acquisition (not locked):
000 = Reserved
001 = 1
010 = 2
R/W
011b
011 = 5
100 = 10
101 = 20
110 = Reserved
111 = Reserved
FEMTOCLOCK^® NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR
28
REVISION E 07/08/15