8T49N282 Datasheet, PDF (11/78 Pages) Integrated Device Technology – Auto and manual input clock selection with hitless switching

8T49N282 DATA SHEET
Power-Saving Modes
To allow the device to consume the least power possible for a given
application, the following functions are included under register
control:
• PLL1 may be shut down.
• Any unused output, including all output divider and phase
adjustment logic, can be individually powered-off.
• Clock gating on logic that is not being used.
Status / Control Signals and Interrupts
General-Purpose I/Os & Interrupts
The 8T49N282 provides eight General Purpose Input / Output
(GPIO) pins for miscellaneous status & control functions. Each GPIO
may be configured as an input or an output. Each GPIO may be
directly controlled from register bits or be used as a predefined
function as shown in Table 4. Note that the default state prior to
configuration being loaded from internal OTP or external EEPROM
will be to set each GPIO to function as an Output Enable.
Table 4. GPIO Configuration
Configured as Input
Fixed Function
GPIO
Pin
Output
Enable
(default)
Clock
Select
General
Purpose
7
OE[7] CSEL1[1] GPI[7]
6
OE[6] CSEL0[1] GPI[6]
5
OE[5]
-
GPI[5]
4
OE[4]
-
GPI[4]
3
OE[3] CSEL1[0] GPI[3]
2
OE[2] CSEL0[0] GPI[2]
1
OE[1]
-
GPI[1]
0
OE[0]
-
GPI[0]
Configured as Output
Fixed
Function
LOS[3]
LOS[2]
LOS[1]
HOLD[1]
LOL[1]
LOS[0]
HOLD[0]
LOL[0]
General
Purpose
GPO[7]
GPO[6]
GPO[5]
GPO[4]
GPO[3]
GPO[2]
GPO[1]
GPO[0]
If used in the Fixed Function mode of operation, the GPIO bits will
reflect the real-time status of their respective status bits as shown in
Table 4. Note that the LOL signal represents the lock status of the
PLL. It does not account for the process of synchronization of the
output dividers associated with that PLL. The output dividers
programmed to operate from that PLL will automatically go through a
re-synchronization process when the PLL locks or re-locks or if the
user triggers a re-sync manually via register bit PLLn_SYN. This
synchronization process may result in a period of instability on the
affected outputs for a duration of up to 350ns after the re-lock (LOL
de-asserts) or the PLLn_SYN bit is de-asserted.
Interrupt Functionality
Interrupt functionality includes an interrupt status flag for each of PLL
Loss-of-Lock Status (LOL[1:0]), PLL Holdover Status (HOLD[1:0])
and Input Reference Status (LOS[3:0]) that is set whenever there is
an alarm on any of those signals. The Status Flag will remain set until
the alarm has been cleared and a ‘1’ has been written to the Status
Flag’s register location or if a reset occurs. Each Status Flag will also
have an Interrupt Enable bit that will determine if that Status Flag is
allowed to cause the Interrupt Status to be affected (enabled) or not
(disabled). All Interrupt Enable bits will be in the disabled state after
reset. The Device Interrupt Status flag and nINT output pin are
asserted if any of the enabled Interrupt Status flags are set.
Device Hardware Configuration
The 8T49N282 supports an internal One-Time Programmable (OTP)
memory that can be pre-programmed at the factory with one
complete device configuration. If the device is set to read a
configuration from an external, serial EEPROM, then the values read
will overwrite the OTP-defined values.
This configuration can be over-written using the serial interface once
reset is complete. Any configuration written via the programming
interface needs to be re-written after any power cycle or reset. Please
contact IDT if a specific factory-programmed configuration is desired.
Device Start-up & Reset Behavior
The 8T49N282 has an internal power-up reset (POR) circuit and a
Master Reset input pin nRST. If either is asserted, the device will be
in the Reset State.
For highly programmable devices, it’s common practice to reset the
device immediately after the initial power-on sequence. IDT
recommends connecting the nRST input pin to a programmable logic
source for optimal functionality. It is recommended that a minimum
pulse width of 10ns be used to drive the nRST input pin.
While in the reset state (nRST input asserted or POR active), the
device will operate as follows:
• All registers will return to & be held in their default states as
indicated in the applicable register description.
• All internal state machines will be in their reset conditions.
• The serial interface will not respond to read or write cycles.
• The GPIO signals will be configured as OE[7:0] inputs.
• All clock outputs will be disabled.
• All interrupt status and Interrupt Enable bits will be cleared,
negating the nINT signal.
Upon the latter of the internal POR circuit expiring or the nRST input
negating, the device will exit reset and begin self-configuration.
The device will load an initial block of its internal registers using the
configuration stored in the internal One-Time Programmable (OTP)
memory. Once this step is complete, the 8T49N282 will check the
register settings to see if it should load the remainder of its
configuration from an external I²C EEPROM at a defined address or
continue loading from OTP. See the section on I²C Boot Initialization
for details on how this is performed.
Once the full configuration has been loaded, the device will respond
to accesses on the serial port and will attempt to lock both PLLs to
the selected sources and begin operation. Once the PLLs are locked,
all the outputs derived from a given PLL will be synchronized and
output phase adjustments can then be applied if desired.
REVISION E 07/08/15
11
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