IDT82V3352 Datasheet, PDF (31/125 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET WAN PLL

IDT82V3352
SYNCHRONOUS ETHERNET WAN PLL
3.12 T0 / T4 APLL
A T0 APLL and a T4 APLL are provided for a better jitter and wander
performance of the device output clocks.
The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0]
/ T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the
better the jitter and wander performance of the T0/T4 APLL output are.
The input of the T0/T4 APLL can be derived from the T0 DPLL out-
puts, as selected by the T0_APLL_PATH[3:0] / T4_APLL_PATH[3:0] bits
respectively.
Both the APLL and DPLL outputs are provided for selection for the
device output.
Table 19: Related Bit / Register in Chapter 3.12
Bit
T0_APLL_BW[1:0]
T4_APLL_BW[1:0]
T0_APLL_PATH[3:0]
T4_APLL_PATH[3:0]
Register
Address (Hex)
T0_T4_APLL_BW_CNFG
6A
T0_DPLL_APLL_PATH_CNFG
55
DPLL_APLL_PATH_CNFG
60
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS
The device supports 2 output clocks and 2 frame sync output signals
altogether.
3.13.1 OUTPUT CLOCKS
The device provides 2 output clocks.
OUT1 outputs a PECL or LVDS signal, as selected by the
OUT1_PECL_LVDS bit. OUT2 outputs a CMOS signal.
The outputs on OUT1 and OUT2 are variable, depending on the sig-
nals derived from the T0 DPLL and T0/T4 APLL outputs, and the corre-
sponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). The derived signal can
be from the T0 DPLL and T0/T4 APLL outputs, as selected by the corre-
sponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). If the signal is derived
from one of the T0 DPLL outputs, please refer to Table 20 for the output
frequency. If the signal is derived from the T0/T4 APLL output, please
refer to Table 21~Table 22 for the output frequency.
The outputs on OUT1 and OUT2 can be inverted, as determined by
the corresponding OUTn_INV bit (n = 1 or 2).
Both the output clocks derived from T0/T4 selected input clock are
aligned with the T0/T4 selected input clock respectively every 125 µs
period.
Table 20: Outputs on OUT1 & OUT2 if Derived from T0 DPLL Outputs
OUTn_DIVIDER[3:0]
(Output Divider) ¹ _{77.76 MHz 12E1}
outputs on OUT1 & OUT2 if derived from T0 DPLL outputs ²
16E1
24T1
16T1
E3
T3
GSM
(26 MHz)
0000
Output is disabled (output low).
0001
0010
12E1
16E1
24T1
16T1
E3
T3
0011
6E1
8E1
12T1
8T1
0100
3E1
4E1
6T1
4T1
0101
2E1
4T1
0110
2E1
3T1
2T1
0111
E1
2T1
1000
E1
T1
1001
T1
1010
64 kHz
1011
8 kHz
1100
2 kHz
1101
400 Hz
1110
1Hz
1111
Output is disabled (output high).
Note:
1. n = 1 or 2. Each output is assigned a frequency divider.
2. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved.
13 MHz
OBSAI
(30.72 MHz)
15.36 MHz
GPS
(40 MHz)
20
10
5
Functional Description
31
March 23, 2009