IDT82V3352 Datasheet, PDF (102/125 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET WAN PLL

IDT82V3352
SYNCHRONOUS ETHERNET WAN PLL
SYNC_PHASE_CNFG - Sync Phase Configuration
Address:7DH
Type: Read / Write
Default Value: XX000000
7
6
5
-
-
SYNC_PH31
4
SYNC_PH30
3
SYNC_PH21
2
SYNC_PH20
1
SYNC_PH11
0
SYNC_PH10
Bit
Name
Description
7-6
-
Reserved.
These bits set the sampling of EX_SYNC3 when EX_SYNC3 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC3 is aligned with the rising edge of the T0 selected input clock.
5-4
SYNC_PH3[1:0]
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
These bits set the sampling of EX_SYNC2 when EX_SYNC2 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC2 is aligned with the rising edge of the T0 selected input clock.
3-2
SYNC_PH2[1:0]
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
These bits set the sampling of EX_SYNC1 when EX_SYNC1 is enabled to synchronize the frame sync output signal. Nomi-
nally, the falling edge of EX_SYNC1 is aligned with the rising edge of the T0 selected input clock.
1-0
SYNC_PH1[1:0]
00: On target. (default)
01: 0.5 UI early.
10: 1 UI late.
11: 0.5 UI late.
Programming Information
102
March 23, 2009