IDT82V3352 Datasheet, PDF (23/125 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET WAN PLL

IDT82V3352
SYNCHRONOUS ETHERNET WAN PLL
• Be cleared when a ‘1’ is written to the corresponding
INn_CMOS_PH_LOCK_ALARM / INn_DIFF_PH_LOCK_
ALARM bit;
• Be cleared after the period (= TIME_OUT_VALUE[5:0] X
MULTI_FACTOR[1:0] in second) which starts from when the
alarm is raised.
The selected input clock with a phase lock alarm is disqualified for T0
DPLL locking.
Table 12: Related Bit / Register in Chapter 3.7
Bit
FAST_LOS_SW
PH_LOS_FINE_LIMT[2:0]
FINE_PH_LOS_LIMT_EN
MULTI_PH_8K_4K_2K_EN
WIDE_EN
PH_LOS_COARSE_LIMT[3:0]
COARSE_PH_LOS_LIMT_EN
T0_DPLL_SOFT_FREQ_ALARM
T0_DPLL_LOCK
DPLL_FREQ_SOFT_LIMT[6:0]
FREQ_LIMT_PH_LOS
DPLL_FREQ_HARD_LIMT[15:0]
TIME_OUT_VALUE[5:0]
MULTI_FACTOR[1:0]
INn_CMOS_PH_LOCK_ALARM (n = 1, 2, or 3)
INn_DIFF_PH_LOCK_ALARM (n = 1 or 2)
PH_ALARM_TIMEOUT
Register
PHASE_LOSS_FINE_LIMIT_CNFG
PHASE_LOSS_COARSE_LIMIT_CNFG
OPERATING_STS
DPLL_FREQ_SOFT_LIMIT_CNFG
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG,
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG
PHASE_ALARM_TIME_OUT_CNFG
IN1_IN2_CMOS_STS, IN3_CMOS_STS
IN1_IN2_DIFF_STS
INPUT_MODE_CNFG
Address (Hex)
5B *
5A *
52
65
67, 66
08
44, 47
45
09
Functional Description
23
March 23, 2009