ICS951464AGLF Datasheet, PDF (3/24 Pages) Integrated Device Technology – Programmable System Clock Chip for ATI RS/RD690 K8™ - based Systems

ICS951464
IDT^TM/ICST^M Programmable System Clock Chip for ATI RS/RD690 K8^TM - based Systems
Pin Description (Continued)
PIN # PIN NAME
29 *CLKREQC#
30 ATIGCLKC1
31 ATIGCLKT1
32 GNDATIG
33 VDDATIG
34 ATIGCLKC0
35 ATIGCLKT0
36 VDDSRC
37 GNDSRC
38 SRCCLKC0
39 SRCCLKT0
40 IREF
41 GNDA
42 VDDA
43 CPUCLK8C1
44 CPUCLK8T1
45 GNDCPU
46 VDDCPU
47 CPUCLK8C0
48 CPUCLK8T0
49 *CLKREQA#
50 GNDHTT
51 HTTCLK0
52 VDDHTT
53 **PD
54 FS2/REF2
55 FS1/REF1
56 FS0/REF0
TYPE
IN
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
PWR
OUT
PWR
IN
I/O
I/O
I/O
DESCRIPTION
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled.
0 = enabled, 1 = tri-stated
Complementary clock of differential ATIGCLK clock pair.
True clock of differential ATIGCLK clock pair.
Ground for ATIG clocks
Power supply ATIG clocks, nominal 3.3V
Complementary clock of differential ATIGCLK clock pair.
True clock of differential ATIGCLK clock pair.
Supply for SRC clocks, 3.3V nominal
Ground pin for the SRC outputs
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
This pin establishes the reference current for the differential current-mode output pairs. This
pin requires a fixed precision resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
Complementary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Ground pin for the CPU outputs
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled.
0 = enabled, 1 = tri-stated
Ground pin for the HTT outputs
3.3V Hyper Transport output
Supply for HTT clocks, nominal 3.3V.
Asynchronous active high input pin used to power down the device. The internal clocks are
disabled and the VCO is stopped.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
IDT^TM/ICST^M Programmable System Clock Chip for ATI RS/RD690 K8^TM - based Systems
3
1211B—09/17/09