ICS951464AGLF Datasheet, PDF (15/24 Pages) Integrated Device Technology – Programmable System Clock Chip for ATI RS/RD690 K8™ - based Systems

ICS951464
IDT^TM/ICST^M Programmable System Clock Chip for ATI RS/RD690 K8^TM - based Systems
Absolute Max
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS Notes
3.3V Core Supply Voltage VDD_A
-
V_DD + 0.5V V
1
3.3V Logic Input Supply
Voltage
VDD_In
-
Storage Temperature
Ts
-
Ambient Operating Temp Tambient
-
Case Temperature
Tcase
-
Input ESD protection HBM ESD prot
-
1_{Guaranteed by design and characterization, not 100% tested in production.}
GND -
0.5
-65
0
2000
V_DD + 0.5V V
1
150
°_C
1
70
°C
1
115
°C
1
V
1
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX UNITS Notes
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Operating Current
Powerdown Current
V_IH
V_IL
I_IH
I_IL1
I_IL2
V_{IH_FS}
3.3 V +/-5%
2
3.3 V +/-5%
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up
resistors
V_SS - 0.3
-5
-5
V_IN = 0 V; Inputs with pull-up
resistors
-200
3.3 V +/-5%
0.7
V_{IL_FS}
I_DD3.3OP
I_DD3.3PD
3.3 V +/-5%
all outputs driven
all diff pairs driven
all differential pairs tri-stated
V_SS - 0.3
V_DD + 0.3 V
1
0.8
V
1
5
uA
1
uA
1
uA
1
V_DD + 0.3 V
1
0.35
V
1
400
mA
1
70
mA
1
12
mA
1
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
Modulation Frequency
Tdrive_PD
Tfall_PD
F_i
L_pin
C_IN
C_OUT
C_INX
T_STAB
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-
assertion of PD to 1st clock
Triangular Modulation
CPU output enable after
PD de-assertion
PD fall time of
14.31818
MHz
2
7
nH
1
5
pF
1
6
pF
1
5
pF
1
1.8
ms
1
30
33
kHz
1
300
us
1
5
ns
1
Trise_PD
PD rise time of
5
ns
1
SMBus Voltage
V_DD
2.7
Low-level Output Voltage
V_OL
@ I_PULLUP
Current sinking at
V_OL = 0.4 V
I_PULLUP
4
SMBCLK/SMBDAT
Clock/Data Rise Time
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
SMBCLK/SMBDAT
Clock/Data Fall Time
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
5.5
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL}
outputs.
IDT^TM/ICST^M Programmable System Clock Chip for ATI RS/RD690 K8^TM - based Systems
1211B—09/17/09
15