ICS951464AGLF Datasheet, PDF (13/24 Pages) Integrated Device Technology – Programmable System Clock Chip for ATI RS/RD690 K8™ - based Systems

ICS951464
IDT^TM/ICST^M Programmable System Clock Chip for ATI RS/RD690 K8^TM - based Systems
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte 13 Pin #
Name
Control Function
Bit 7
-
SSP7
Bit 6
-
SSP6
Bit 5
-
SSP5
Bit 4
-
SSP4
Spread Spectrum Programming
Bit 3
-
SSP3
b(7:0)
Bit 2
-
SSP2
Bit 1
-
SSP1
Bit 0
-
SSP0
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte 14 Pin #
Name
Control Function
Bit 7
Reserved
Bit 6
-
Bit 5
-
SSP14
SSP13
Bit 4
-
Bit 3
-
Bit 2
-
SSP12
SSP11
SSP10
Spread Spectrum Programming
b(14:8)
Bit 1
-
SSP9
Bit 0
-
SSP8
Type
RW
RW
RW
RW
RW
RW
RW
SMBus Table: ATIG PLL VCO Frequency Control Register
Byte 15 Pin #
Name
Control Function
Bit 7
-
N Div8
N Divider Prog bit 8
Bit 6
-
N Div9
N Divider Prog bit 9
Bit 5
-
M Div5
Bit 4
-
M Div4
Bit 3
-
Bit 2
-
M Div3
M Div2
M Divider Programming bits
Bit 1
-
M Div1
Bit 0
-
M Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: ATIG PLL VCO Frequency Control Register
Byte 16 Pin #
Name
Control Function
Bit 7
-
N Div7
Bit 6
-
N Div6
Bit 5
-
N Div5
Bit 4
-
Bit 3
-
N Div4
N Div3
N Divider Programming b(7:0)
Bit 2
-
N Div2
Bit 1
-
N Div1
Bit 0
-
N Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: ATIG PLL Spread Spectrum Control Register
Byte 17 Pin #
Name
Control Function
Bit 7
-
SSP7
Bit 6
-
SSP6
Bit 5
-
SSP5
Bit 4
-
SSP4
Spread Spectrum Programming
Bit 3
-
SSP3
b(7:0)
Bit 2
-
SSP2
Bit 1
-
SSP1
Bit 0
-
SSP0
Type
RW
RW
RW
RW
RW
RW
RW
RW
IDT^TM/ICST^M Programmable System Clock Chip for ATI RS/RD690 K8^TM - based Systems
13
0
1
PWD
X
These Spread Spectrum bits ^X
in Byte 13 and 14 will program X
the spread pecentage. It is X
recommended to use ICS X
Spread % table for spread _X
programming.
X
X
0
1
PWD
0
X
These Spread Spectrum bits _X
in Byte 13 and 14 will program _X
the spread pecentage. It is
recommended to use ICS
X
Spread % table for spread ^X
programming.
X
X
0
1
PWD
X
The decimal representation of _X
M and N Divier in Byte 17 and _X
18 will configure the VCO
frequency. Default at power
X
up = Byte 0 Rom table. VCO ^X
Frequency = 14.318 x
X
[NDiv(9:0)+8] / [MDiv(5:0)+2] ^X
X
0
1
PWD
X
The decimal representation of _X
M and N Divier in Byte 17 and _X
18 will configure the VCO
frequency. Default at power
X
up = Byte 0 Rom table. VCO ^X
Frequency = 14.318 x
X
[NDiv(9:0)+8] / [MDiv(5:0)+2] ^X
X
0
1
PWD
X
These Spread Spectrum bits ^X
in Byte 19 and 20 will program X
the spread pecentage. It is X
recommended to use ICS X
Spread % table for spread _X
programming.
X
X
1211B—09/17/09