ICS854S202I-01 Datasheet, PDF (3/17 Pages) Integrated Device Technology – 12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

ICS854S202I-01
12:2, DIFFERENTIAL-LVDS MULTIPLEXER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS (CONTINUED)
Number
Name
Type
Description
42
OEB
Input
Pullup
Output enable pin. Controls enabling and disabling of QB/nQB
outputs. LVCMOS/LVTTL internface levels. See Table 3A.
44
CLK0
Input Pullup Non-inverting differential clock input.
45
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input. V_DD/2 default when left floating.
47
CLK1
Input Pullup Non-inverting differential clock input.
48
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock input. V /2 default when left floating.
DD
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3B. OEA, OEB CONTROL INPUT FUNCTION TABLE
Input
OEA, OEB
0
1
Output
QA/nQA, QB/nQB
Disabled (Logic LOW)
Active
IDT^™ / ICS^™ LVDS MULTIPLEXER
3
ICS854S202AYI-01 REV. A JANUARY 8, 2007