ICS849N202I Datasheet, PDF (3/39 Pages) Integrated Device Technology – FemtoClock® NG Universal Frequency Translator

ICS849N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Table 1. Pin Descriptions
Number
1
2
3, 7, 13, 29
Name
XTAL_IN
XTAL_OUT
V_CC
4
CLK_SEL
5
6
8, 21, 35
9
10
11, 19,
20, 32
CLK0
nCLK0
V_EE
CLK1
nCLK1
nc
12
PLL_BYPASS
14
SDATA
15
SCLK
16
CONFIG
17
18
22
23, 24
25
26, 27
28
30
S_A1
S_A0
OE1
nQ1, Q1
V_CCO
nQ0, Q0
OE0
LOCK_IND
31
CLK_ACTIVE
Type
Input
Power
Input
Pulldown
Input
Input
Power
Input
Input
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Crystal Oscillator interface designed for 12pF parallel resonant crystals.
XTAL_IN (pin 1) is the input and XTAL_OUT (pin 2) is the output.
Core supply pins. All must be either 3.3V or 2.5V.
Input clock select. Selects the active differential clock input. LVCMOS/LVTTL
interface levels.
0 = CLK0, nCLK0 (default)
1 = CLK1, nCLK1
Non-inverting differential clock input.
Inverting differential clock input. V_CC/2 default when left floating (set by the
internal pullup and pulldown resistors).
Negative supply pins.
Non-inverting differential clock input.
Inverting differential clock input. V_CC/2 default when left floating (set by the
internal pullup and pulldown resistors).
Unused
No connect. These pins are to be left unconnected.
Input
I/O
Input
Input
Input
Input
Input
Output
Power
Output
Input
Output
Output
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Bypasses the VCXO PLL. In bypass mode, outputs are clocked off the falling
edge of the input reference. LVCMOS/LVTTL interface levels.
0 = PLL Mode (default)
1 = PLL Bypassed
I²C Data Input/Output. Open drain.
I²C Clock Input. LVCMOS/LVTTL interface levels.
Configuration Pin. Selects between one of two factory programmable pre-set
power-up default configurations. The two configurations can have different
output/input frequency translation ratios, different PLL loop bandwidths, etc.
These default configurations can be overwritten after power-up via I²C if the
user so desires. LVCMOS/LVTTL interface levels.
0 = Configuration 0 (default)
1 = Configuration 1
I²C Address Bit 1. LVCMOS/LVTTL interface levels.
I²C Address Bit 0. LVCMOS/LVTTL interface levels.
Active High Output Enable for Q1, nQ1. LVCMOS/LVTTL interface levels.
0 = Output pins high-impedance
1 = Output switching (default)
Differential output. Output type is programmable to LVDS or LVPECL interface
levels.
Output supply pins for Q1, nQ1 and Q0, nQ0 outputs. Either 2.5V or 3.3V.
Differential output. Output type is programmable to LVDS or LVPECL interface
levels.
Active High Output Enable for Q0, nQ0. LVCMOS/LVTTL interface levels.
0 = Output pins high-impedance
1 = Output switching (default)
Lock Indicator - indicates that the PLL is in a locked condition. LVCMOS/LVTTL
interface levels.
Indicates which of the two differential clock inputs is currently selected.
LVCMOS/LVTTL interface levels.
0 = CLK0, nCLK0 differential input pair
1 = CLK1, nCLK1 differential input pair
ICS849N202CKI REVISION A SEPTEMBER 26, 2011
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©2011 Integrated Device Technology, Inc.