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ICS849N202I Datasheet, PDF (27/39 Pages) Integrated Device Technology – FemtoClock® NG Universal Frequency Translator | |||
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ICS849N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50â¦
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 8A and 8B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
Zo = 50â¦
3.3V
+
LVPECL
Zo = 50â¦
R1
50â¦
RTT =
1
((VOH + VOL) / (VCC â 2)) â 2
* Zo
_
Input
R2
50â¦
VCC - 2V
RTT
3.3V
LVPECL
3.3V
R3
R4
125â¦
125â¦
3.3V
Zo = 50â¦
+
Zo = 50â¦
R1
84â¦
_
R2
84â¦
Input
Figure 8A. 3.3V LVPECL Output Termination
Figure 8B. 3.3V LVPECL Output Termination
ICS849N202CKI REVISION A SEPTEMBER 26, 2011
27
©2011 Integrated Device Technology, Inc.
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