ICS84330CI Datasheet, PDF (3/20 Pages) Integrated Circuit Systems – 720MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ICS84330CI Data Sheet
720MHZ, CRYSTAL-TO-LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Name
V_CCA
XTAL1, XTAL2
XTAL_SEL
OE
nP_LOAD
Type
Power
Input
Input
Input
Pullup
Pullup
Pullup
Description
Analog supply pin.
Crystal oscillator interface. XTAL1 is an oscillator input, XTAL2 is an oscillator output.
Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW.
LVCMOS / LVTTL interface levels.
Output enable. LVCMOS / LVTTL interface levels.
Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and
when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
M0, M1, M2
M3, M4, M5
M6, M7, M8
N0, N1
V_EE
TEST
V_CC
nFOUT, FOUT
nc
FREF_EXT
S_CLOCK
S_DATA
S_LOAD
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS /
LVTTL interface levels.
Input
Power
Output
Power
Output
Unused
Input
Input
Input
Input
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
Single-ended LVPECL interface levels.
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
No connect.
PLL reference input. LVCMOS / LVTTL interface levels.
Clocks the serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS84330CVI REVISION A JANUARY 7, 2011
3
©2011 Integrated Device Technology, Inc.