ICS84330CI Datasheet, PDF (12/20 Pages) Integrated Circuit Systems – 720MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ICS84330CI Data Sheet
720MHZ, CRYSTAL-TO-LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout example:
All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors C3 and C4, as close as possible to
the power pins. If space allows, placement of the decoupling
capacitor on the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the V_CCA pin as possible.
Clock Traces and Termination
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the clock
signal is less tolerant to poor signal integrity than other signals. Any
ringing on the rising or falling edge or excessive ring back can cause
system failure. The shape of the trace and the trace delay might be
restricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
• The differential 50 output traces should have the same
length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever possible,
avoid placing vias on the clock traces. Placement of vias on the
traces can affect the trace characteristic impedance and hence
degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace widths
between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the clock
trace pair.
• The matching termination resistors should be located as close
to the receiver input pins as possible.
Crystal
The crystal X1 should be located as close as possible to the pins 4
(XTAL1) and 5 (XTAL2). The trace length between the X1 and U1
should be kept to a minimum to avoid unwanted parasitic inductance
and capacitance. Other signal traces should not be routed near the
crystal traces.
C1
U1
X1
C2
PIN 2
PIN 1
C11 C16
VCCA
R7
GND
VCC
VCCA
VIA
Signals
Traces
C3
C4
50 Ohm
Traces
Figure 6B. ICS84330CI PCB Board Layout for ICS84330CI
ICS84330CVI REVISION A JANUARY 7, 2011
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©2011 Integrated Device Technology, Inc.