ICS84330CI Datasheet, PDF (2/20 Pages) Integrated Circuit Systems – 720MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ICS84330CI Data Sheet
720MHZ, CRYSTAL-TO-LVPECL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 6, NOTE 1.
The ICS84330CI features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
quartz crystal is used as the input to the on-chip oscillator. The output
of the oscillator is divided by 16 prior to the phase detector. With a
16MHz crystal, this provides a 1MHz reference frequency. The VCO
of the PLL operates over a range of 250MHz to 720MHz. The output
of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency by adjusting the VCO
control voltage. Note that for some values of M (either too high or too
low), the PLL will not achieve lock. The output of the VCO is scaled
by a divider prior to being sent to each of the LVPECL output buffers.
The divider provides a 50% output duty cycle.
The programmable features of the ICS84330CI support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial. Figure 1 shows the timing
diagram for each mode. In parallel mode the nP_LOAD input is LOW.
The data on inputs M0 through M8 and N0 through N1 is passed
directly to the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. The TEST output is Mode 000 (shift register out)
when operating in the parallel input mode. The relationship between
the VCO frequency, the crystal frequency and the M divider is defined
as follows:
fVCO = fXTAL x 2M
16
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock are defined as 125  M 
360. The frequency out is defined as follows:
fout = fVCO = fXTAL x 2M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider when S_LOAD transitions from
LOW-to-HIGH. The M divide and N output divide values are latched
on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,
data at the S_DATA input is passed directly to the M divider on each
rising edge of S_CLOCK. The serial mode can be used to program
the M and N bits and test bits T2:T0. The internal registers T2:T0
determine the state of the TEST output as follows in the table below:
T2
T1
T0 TEST Output
f_OUT
0
0
0 Shift Register Out
f_OUT
0
0
1 HIGH
f_OUT
0
1
0 PLL Reference XTAL ÷16
f_OUT
0
1
1 (VCO ÷ M)/2 (non 50% Duty Cycle M Divider)
f_OUT
1
0
0 f_OUT, LVCMOS Output Frequency < 200MHz
f_OUT
1
0
1 LOW
f_OUT
1
1
0 (S_CLOCK ÷ M)/2 (non 50% Duty Cycle M Divider) S_CLOCK ÷ N Divider
1
1
1 f_OUT ÷ 4
f_OUT
S_CLOCK
SERIAL LOADING
S_DATA
S_LOAD
T2 T1
tt
SH
T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
nP_LOAD
M0:M8, N0:N1
t
S
PARALLEL LOADING
M, N
nP_LOAD
nP_LOAD
Figure 1. Parallel & Serial Load Operations
tt
SH
Time
ICS84330CVI REVISION A JANUARY 7, 2011
2
©2011 Integrated Device Technology, Inc.