ICS2008B Datasheet, PDF (3/22 Pages) Integrated Circuit Systems – SMPTE Time Code Receiver/Generator

ICS2008B
Pin Descriptions
PIN NUMBER
TQFP PLCC
PIN
NAME
12, 10 18, 16 Y1, Y2
11, 9
15
13
14
8
7
41
42
44
43
1
20
22
21
18
16
17
19
4
3
2
24, 23
27
30
25
26
40
38–31
39
5
6
29
28
17, 15 C1, C2
21
19
20
14
13
3
4
6
5
7
26
28
27
24
22
23
25
10
9
8
30, 29
33
36
31
32
2
44–37
1
11
12
35
34
DTHRESH
STHRESH
CTHRESH
Y OUT
C OUT
FRAME
CLICK
LTCIN+
LTCIN–
LTCOUT
LRCLK
VITCOUT
VITCGATE
TxD
RxD
CTS*
RTS*
XTAL1
XTAL2
LFC
A1-A0
IOR*
IOW*
SMPTECS*
UARTCS*
RESET
D7-D0
INTR
AVDD
AVSS
VDD
VSS
TYPE
DESCRIPTION
AI
Video inputs from camera or other source. NOTE: This is also the Y
(Luma) input for S-VHS and HI-8 systems.
AI
C (Chroma) inputs for S-VHS and HI-8 systems. In NTSC systems, this
pin should be tied to its respective Y input.
AI Data Threshold bypass input.
AI SYNC Threshold bypass input.
AI Clamp Threshold bypass input.
AO Video output. This is also the Y (Luma) output in S-Video mode.
AO C (Chroma) output for S-VHS and HI-8 systems.
AI _{Color Frame A/B input. This input is self biased (See Applications).}
AI LTC SYNC input. This input is self biased (See Applications).
AI SMPTE LTC input+. This input is self biased (See Applications).
AI SMPTE LTC input–. This input is self biased (See Applications).
AO SMPTE LTC output
O SMPTE LTC receive clock output.
O SMPTE VITC output to video mixer circuit.
O VITC gate indicates VITC code is being output for video overlay.
O UART Transmit data
I UART Receive data
I Clear to Send
O Ready to Send
I 14.318 MHz crystal input.
O 14.318 MHz crystal oscillator output.
AI Tie to +5 VDC
I Address bus
I Read Enable (active low)
I Write Enable (active low)
I SMPTE port chip select (active low)
I UART chip select (active low)
I Master reset (active high)
I/O Bi-directional data bus
O Interrupt Request (active high)
P Analog VDD
P Analog Ground
P Digital VDD
P Digital
TYPE:
A – Analog • P – Power • I – Input • O – Output 2008 2008B ICS2008
3
ICS2008B