ICS2008B Datasheet, PDF (10/22 Pages) Integrated Circuit Systems – SMPTE Time Code Receiver/Generator

ICS2008B
Timer Control Registers IR3C & IR3D
These two registers control the interrupt timer. It should be
noted that IR3C is a write only register, while IR3D is a read/
write register.
7 6 5 4 3 2 1 0 _IR3C
Timer Value (w/o)
TMRVAL [7:0]
76543210
IR3D
Timer Control (r/w)
TMRVAL [9:8]
Reserved
CLKSEL
(00-LXCLK, 01-LRCLK)
(10-reserved, 11-100 kHz)
RUN (1-run, 0-stop)
TMRVAL — These ten bits set the divider value for the inter-
rupt timer. The interrupt rate is the input clock rate divided by
the value plus one.
Interrupt Rate = CLOCK /(TMRVAL+1)
CLKSEL — This 2 bit field selects the clock source for the
interrupt timer. The 100 kHz input is actually 100.126 kHz. It
is the crystal frequency divided by 143.
RUN — This bit starts and stops the timer. When set to one,
the timer is running. When set to zero, the timer is stopped.
76543210
IR3E
Burn-in Window Attributes
BLINK [1-blink, 0 -stable]
WINATTR
(00 -white on black)
(01-black on white)
(10-white on background)
(11-black on background)
(10-reserved, 11-100 kHz)
WINSIZE
(1-large, 0-normal)
HSF (1-enable, 0-disable)
Reserved
BLINK — This bit controls the upper dot of the right-most
colon in the burn-in-window. When set to zero, the upper dot
is on. When set to one, it is off. This feature can be used to
indicate odd and even fields in the time code display window.
WINATTR — These two bits control the color of the
characters and the background in the burn-in window. When
the most significant bit of this field is a one, the background is
the incoming video.
WINSIZ — This bit controls the size of the burn-in window.
The difference in size between a large and a normal-sized
window is 32 scan lines high, while a large window is 64 scan
lines high.
HSF (Head Switch Filter) — When set to one, this bit causes
the clamp circuit to ignore head switch transients and
horizontal sync during the last six to seven lines before the
vertical front porch. Otherwise, the clamp circuit responds
always.
LTC Soft Sync IR3F
IR3f is not a register at all. It is simply an address which,
when written and the LTC SYNC select is set for Soft SYNC,
generates LTC SYNC for the LTC transmitter.
7 6 5 4 3 2 1 0 _IR3F
LTC Soft SYNC (w/o, no data)
ICS2008B
10