ICS2008B Datasheet, PDF (12/22 Pages) Integrated Circuit Systems – SMPTE Time Code Receiver/Generator

ICS2008B
UART Registers
The UART emulates a 6850. Since the UART is tailored to
MIDI applications, some of the generic 6850 functions have
been omitted. The registers described below reflect that.
The two UART registers, Command/Status and Data, are
accessible to the processor as shown in the following map.
UARTCS* A1 A0
REGISTER
0
X 0 UART Command/Status Register
76543210
UART0 (read)
UART2 Status Register
RBF – Receive Buffer Full (1-Full)
TBE – Transmit Buffer Empty (1-Empty)
Reserved
CTS – Clear-to-Send (0-Active)
FE – Framing Error (1-Error)
OV – Receiver Overrun (1-Overrun)
Reserved
IRQ – Interrupt Request (1-Active)
0
X 1 UART Data Register
UART Command/Status Register
7 6 5 4 3 2 1 0 _{UART0 (write)}
UART Command Register
Bit Rate (00 - 9600, 10 - 38.4K)
(01 - 31.25K, 11 - Reset)
Reserved
TC1, TC0 Transmit Control
00 - RTS* – low, Tx IRQ disabled
01 - RTS* – low, Tx IRQ enabled
10 - RTS* – high, Tx IRQ disabled
11 - RTS* – low, Transmit BREAK,
Tx IRQ disabled
RIE - Receive Interrupt Enable
RBF — Bit 0, Receive Buffer Full, is set to 1 when read data
is available in the UART data register. It is cleared to 0 when
the UART data register is read.
TBE — Bit 1, Transmit Buffer Empty, is cleared to 0 when
data is written to the UART data register. It is set to 1 when the
UART transfers that data to its output shift register.
CTS — Bit 3, Clear-to-Send, is an active low status bit
indicating the state of the CTS* input pin. A 0 in this bit
position indicates that the modem or receiving device is ready
to receive characters. A 1 indicates not ready. When CTS is
inactive, 1, TBE is held at 0, the not-empty state.
FE — Bit 4, Framing Error, when set to 1, indicates that the
receive character was improperly framed by the start and stop
bits. It is detected by the absence of the first stop bit. This
indicator is valid as long as the character data is valid.
Bit Rate — This field selects the bit rate for data transmit and
receive. After a master reset, its value is 11. One of the three
bit rates must be selected in order to start the UART’s
operation. Writing a 11 will reset the UART.
TC1, TC0 — Bits 6 and 5, Transmit Control, provide control
for transmit interrupt (when TBE is true), RTS control, and
transmit BREAK level.
RIE — Bit 7, Receive interrupt enable, when set to one,
enables the UART to interrupt the processor when the receive
buffer is full or a receive overrun has occurred.
OV — Bit 5, Receiver Overrun, is an error flag indicating that
one or more characters in the data stream has been lost. It is set
to 1 when a new character overwrites an old character which
has not been read. The overrun error is cleared to 0 when a
character is read from the UART data register.
IRQ — Bit 7, Interrupt Request, is a status bit which reflects
the state of the interrupt request from the UART to the
processor. When IRQ is 1, an interrupt is pending. Otherwise,
no interrupt is pending.
The UART data register is actually two registers, a transmit
buffer and a receive buffer. Writing to the data register causes
the transmit buffer to be written. Reading from the data regis-
ter causes the receive buffer to be read.
7 6 5 4 3 2 1 0 _UART1
UART Data Register
ICS2008B
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