8T49N281_16 Datasheet, PDF (28/67 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N281 Datasheet
Table 6L. Analog PLL Control Register Bit Field Locations and Descriptions
Please contact IDT through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular
user configuration.
Analog PLL Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
00AC
CPSET[2:0]
RS[1:0]
CP[1:0]
WPOST
00AD
Rsvd
SYN_MODE
Rsvd
DLCNT
DBITM
00AE
Rsvd
VCOMAN
DBIT1[4:0]
00AF
Rsvd
DBIT2[4:0]
Bit Field Name
CPSET[2:0]
RS[1:0]
CP[1:0]
WPOST
DLCNT
DBITM
VCOMAN
DBIT1[4:0]
DBIT2[4:0]
SYN_MODE
Rsvd
Field Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Analog PLL Control Register Block Field Descriptions
Default Value Description
100b
Charge Pump Current Setting for Analog PLL:
000 = 110 µA
001 = 220 µA
010 = 330 µA
011 = 440 µA
100 = 550 µA
101 = 660 µA
110 = 770 µA
111 = 880 µA
Internal Loop Filter Series Resistor Setting for Analog PLL:
00 = 330 
01b
01 = 640 
10 = 1.2 k
11 = 1.79 k
Internal Loop Filter Parallel Capacitor Setting for Analog PLL:
00 = 40 pF
01b
01 = 80 pF
10 = 140 pF
11 = 200 pF
Internal Loop Filter 2nd-Pole Setting for Analog PLL:
1b
0 = Rpost = 497 , Cpost = 40 pF
1 = Rpost = 1.58k , Cpost = 40 pF
Digital Lock Count Setting for Analog PLL:
Value should be set to 0 (1ppm accuracy) if external capacitor value is >95nF,
1b
otherwise set to 1.
0 = 1 ppm accuracy
1 = 16 ppm accuracy
Digital Lock Manual Override Setting for Analog PLL:
0b
0 = Automatic Mode
1 = Manual Mode
Manual Lock Mode VCO Selection Setting for Analog PLL:
1b
0 = VCO2
1 = VCO1
01011b Manual Mode Digital Lock Control Setting for VCO1 in Analog PLL.
00000b Manual Mode Digital Lock Control Setting for VCO2 in Analog PLL.
Frequency Synthesizer Mode Control for PLL:
0 = PLL jitter attenuates and translates one or more input references
0b
1 = PLL synthesizes output frequencies using only the crystal as a reference
Note that the STATE0[1:0] field in the Digital PLL Control Register must be set to
Force Freerun state.
-
Reserved. Always write 0 to this bit location. Read values are not defined.
©2016 Integrated Device Technology, Inc.
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Revision 7, October 26, 2016