8T49N281_16 Datasheet, PDF (20/67 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N281 Datasheet
Bit Field Name
DSM_ORD[1:0]
DCXOGAIN[1:0]
DITHGAIN[2:0]
Rsvd
Digital PLL Feedback Configuration Register Block Field Descriptions
Field Type Default Value Description
Delta-Sigma Modulator Order for Digital PLL:
00 = Delta-Sigma Modulator disabled
R/W
11b
01 = 1st order modulation
10 = 2nd order modulation
11 = 3rd order modulation
Multiplier applied to instantaneous frequency error before it is applied to the Digitally
Controlled Oscillator in Digital PLL:
R/W
01b
00 = 0.5
01 = 1
10 = 2
11 = 4
Dither Gain setting for Digital PLL:
000 = no dither
001 = Least Significant Bit (LSB) only
010 = 2 LSBs
R/W
000b
011 = 4 LSBs
100 = 8 LSBs
101 = 16 LSBs
110 = 32 LSBs
111 = 64 LSBs
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
NOTE 1: Settings other than “00” may result in a significant increase in initial lock time.
©2016 Integrated Device Technology, Inc.
20
Revision 7, October 26, 2016