8V44N4614 Datasheet, PDF (25/31 Pages) Integrated Device Technology – Clock generator for wireless base-band systems

8V44N4614 DATA SHEET
Schematic Example
Figure 5 (next page) shows an example 8V44N4614 application
schematic in which the device is operated at V_DD = 3.3V.
This example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set for the application.
Three different differential terminations are depicted. QA0 is the
standard LVDS termination. QA1 is an example demonstrating how
the IDT LVDS outputs can be directly AC coupled to IDT CLK, nCLK
clock receiver inputs where the internal bias resistors of the receiver
guarantee that the AC coupled LVDS clock is within the common
mode range of the receiver. QA2 is an LVPECL Delta termination
equivalent to the Wye termination shown on the CLK, nCLK input.
This termination is easier to layout in comparison to the Wye
termination.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 8V44N4614 provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL. The Murata BLM18BB221SN1B ferrite
bead shown in the schematic was selected for the flat frequency
response realized with the associated filter capacitors. The rated
current for this bead is 450mA which will accommodate the maximum
current for each power filter.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the 10
ohm V_CCA resistor and the 0.1uF capacitor in each power pin filter
should be placed on the device side. The other components can be
on the opposite side of the PCB. Pull-up and pull-down resistors to
set configuration pins can all be placed on the PCB side opposite the
device side to free up device side area if necessary.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
For additional layout recommendations and guidelines, contact
[e-mail].
REVISION 1 02/25/15
25
FEMTOCLOCK^® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER