8V44N4614 Datasheet, PDF (22/31 Pages) Integrated Device Technology – Clock generator for wireless base-band systems

8V44N4614 DATA SHEET
LVDS Driver Termination
A general LVDS interface is shown in Figure 2A. Standard
termination for LVDS type output structure requires both a 100
parallel resistor at the receiver and a 100 differential transmission
line environment. In order to avoid any transmission line reflection
issues, the 100 resistor must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 2A can be used
with either type of output structure. If using a non-standard
termination, it is recommended to contact IDT and confirm if the
output is a current source or a voltage source type structure. In
addition, since these outputs are LVDS compatible, the amplitude
and common mode input range of the input receivers should be
verified for compatibility with the output.
LVDS
Driver
Z_O  Z_T
Figure 2A. Standard Termination
LVDS
Z_T
Receiver
LVDS
Driver
Z_O  Z_T
Figure 2B. Optional Termination
LVDS Driver Termination
Z_T
2 _LVDS
C
Z_T Receiver
2
FEMTOCLOCK^® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
22
REVISION 1 02/25/15