ICS9LPRS462 Datasheet, PDF (20/23 Pages) Integrated Device Technology – Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs

ICS9LPRS462
Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs
RESET_IN# - Assertion (transition from '1' to '0')
Asserting RESET_IN pin stops all the outputs including CPU, SRC, ATIG, PCI and USB with the REF[2:0] running.
The pin is a Schmitt trigger input with debouncing. After it is triggered, REF clocks will wait for two clock cycle to
ensure the RESET_IN is asserted. Then, it will take 3uS for the clocks to stop without glitches. The clock chip will
be power down and re-power up, and SMBus will be reloaded. It will take no more than 2.5mS for the clocks to come
out with correct frequencies and no glitches.
** Deassertion of RESET_IN# (transition from '0' to '1') has NO effect on the clocks.
RESET_IN#
2 clock
cycles
3 uS max
2.5mS max
REF [2:0]
*CLKS
IDT^TM/ICS^TM Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs
20
1378A—04/07/08