ICS9LPRS462 Datasheet, PDF (17/23 Pages) Integrated Device Technology – Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs

ICS9LPRS462
Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs
SMBus Table: Byte Count Register
Byte 8 Pin #
Name
Bit 7
-
BC7
Bit 6
-
BC6
Bit 5
-
BC5
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
Bit 0
-
BC0
Control Function
Byte Count Programming b(7:0)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
0
0
Writing to this register will 0
congiure how many bytes will 0
be read back, default is 9
1
bytes.
0
0
1
SMBus Table: REF2, 48MHz Output Strength Control and ATIG Frequency Select Register
Byte 9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Pin #
54
7
6
-
-
-
Name
REF2Str
48MHz_1Str
48MHz_0Str
ATIG FS3
ATIG FS2
ATIG FS1
Control Function
REF2 Strength Control
48MHz_1 Strength Control
48MHz_0 Strength Control
Reserved
ATIG Freq Select Bit 3
ATIG Freq Select Bit 2
ATIG Freq Select Bit 1
Type
RW
RW
RW
RW
RW
RW
0
1
1X
2X
1X
2X
1X
2X
See Table 3: ATIG
Frequency Selection Table
Bit 0
-
ATIG FS0
ATIG Freq Select Bit 0
RW
PWD
1
1
1
0
0
0
0
0
SMBus Table: PLLs M/N Programming Enable and REF1, REF0 Output Strength Control Register
Byte 10 Pin #
Name
Control Function
Type
0
Bit 7
-
M/N_EN
PLLs M/N Programming Enable
RW
Disable
Bit 6
55
REF1Str
REF1 Strength Control
RW
1X
Bit 5
56
REF0Str
REF0 Strength Control
RW
1X
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Reserved
Bit 0
Reserved
1
Enable
2X
2X
PWD
0
1
1
0
0
0
0
0
SMBus Table: CPU PLL VCO Frequency Control Register
Byte 11 Pin #
Name
Control Function
Bit 7
-
N Div8
N Divider Prog bit 8
Bit 6
-
N Div 9
N Divider Prog bit 9
Bit 5
-
M Div5
Bit 4
-
M Div4
Bit 3
-
Bit 2
-
M Div3
M Div2
M Divider Programming bits
Bit 1
-
M Div1
Bit 0
-
M Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
The decimal representation of ^X
M and N Divier in Byte 11 and ^X
12 will configure the VCO
X
frequency. Default at power X
up = latch-in or Byte 0 Rom X
table. VCO Frequency =
X
14.318 x [NDiv(9:0)+8] /
X
[MDiv(5:0)+2]
X
SMBus Table: CPU PLL VCO Frequency Control Register
Byte 12 Pin #
Name
Control Function
Bit 7
-
N Div7
Bit 6
-
N Div6
Bit 5
-
N Div5
Bit 4
-
Bit 3
-
N Div4
N Div3
N Divider Programming b(7:0)
Bit 2
-
N Div2
Bit 1
-
N Div1
Bit 0
-
N Div0
IDT^TM/ICS^TM Low Power Clock for ATI RS/RD600 series chipsets for AMD CPUs
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
The decimal representation of ^X
M and N Divier in Byte 11 and ^X
12 will configure the VCO
X
frequency. Default at power X
up = latch-in or Byte 0 Rom X
table. VCO Frequency =
X
14.318 x [NDiv(9:0)+8] /
X
[MDiv(5:0)+2]
X
1378A—04/07/08
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