ICS9UMS9633BW Datasheet, PDF (2/18 Pages) Integrated Device Technology – ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE

ICS9UMS9633BW
ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE
Datasheet
SSOP Pin Description
PIN #
PIN NAME
1 REF
2 GNDREF
3 VDDCORE_3.3
4 FSC_L
5 TEST_MODE
6 TEST_SEL
7 SCLK
8 SDATA
9 VDDCORE_3.3
10 VDDIO_1.5
11 DOT96C_LPR
12 DOT96T_LPR
13 GNDDOT
14 GNDLCD
15 LCD100C_LPR
16 LCD100T_LPR
17 VDDIO_1.5
18 VDDCORE_3.3
19 *CR#0
20 GNDSRC
21 SRCC0_LPR
22 SRCT0_LPR
23 *CR#1
24 VDDCORE_3.3
TYPE
DESCRIPTION
OUT 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
PWR 3.3V power for the PLL core
IN ^{Low threshold input for CPU frequency selection. Refer to input electrical}
characteristics for Vil_FS and Vih_FS values.
IN ^{TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode}
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
IN 1 = All outputs are tri-stated for test
0 = All outputs behave normally.
IN Clock pin of SMBus circuitry, 5V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 3.3V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
OUT ^{Complementary clock of low power differential pair for 96.00MHz DOT clock. No}
50ohm resistor to GND needed. No Rs needed.
OUT ^{True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor}
to GND needed. No Rs needed.
PWR Ground pin for DOT clock output
PWR Ground pin for LCD clock output
OUT ^{Complementary clock of low power differential pair for LCD100 SS clock. No 50ohm}
resistor to GND needed. No Rs needed.
OUT ^{True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to}
GND needed. No Rs needed.
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
IN Clock request for SRC0, 0 = enable, 1 = disable
PWR Ground pin for the SRC outputs
OUT ^{Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm}
series resistor. No 50ohm resistor to GND needed.
OUT ^{True clock of differential 0.8V push-pull SRC output with integrated 33ohm series}
resistor. No 50ohm resistor to GND needed.
IN Clock request for SRC1, 0 = enable, 1 = disable
PWR 3.3V power for the PLL core
IDT^TM/ICS^TM Ultra Mobile PC Clock for Automotive use
2
1425A—09/02/09