ICS9UMS9633BW Datasheet, PDF (11/18 Pages) Integrated Device Technology – ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE

ICS9UMS9633BW
ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE
Datasheet
Byte
Bit(s)
7
6
5
4
3
2
1
0
2
Pin #
Output Enable Register
Name
Description
CPU0 Enable
This bit controls whether the CPU[0] output buffer
is enabled or not.
CPU1 Enable
This bit controls whether the CPU[1] output buffer
is enabled or not.
CPU2 Enable
This bit controls whether the CPU[2] output buffer
is enabled or not.
SRC0 Enable
This bit controls whether the SRC[0] output buffer
is enabled or not.
SRC1 Enable
This bit controls whether the SRC[1] output buffer
is enabled or not.
SRC2 Enable
This bit controls whether the SRC[2] output buffer
is enabled or not.
DOT Enable
This bit controls whether the DOT output buffer is
enabled or not.
LCD100 Enable
This bit controls whether the LCD output buffer is
enabled or not.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
1
Default
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
1 = Enabled
1
Byte
Bit(s)
7
6
5
4
3
2
1
0
3 Output Control Register
Pin #
Name
Description
Reserved
Reserved
REF Enable
This bit controls whether the REF output buffer is
enabled or not.
Type
RW
REF Slew
These bits control the edge rate of the REF clock. RW
This bit controls whether the CPU[0] output buffer
CPU0 Stop Enable ^{is free-running or stoppable. If it is set to stoppable} RW
the CPU[0] output buffer will be disabled with the
assertion of CPU_STP#.
This bit controls whether the CPU[1] output buffer
CPU1 Stop Enable ^{is free-running or stoppable. If it is set to stoppable} RW
the CPU[1] output buffer will be disabled with the
assertion of CPU_STP#.
This bit controls whether the CPU[2] output buffer
is free-running or stoppable. If it is set to stoppable
CPU2 Stop Enable _{the CPU[2] output buffer will be disabled with the} RW
assertion of CPU_STP#.
0
1
0 = Disabled 1 = Enabled
00 = Slow Edge Rate
01 = Medium Edge Rate
10 = Fast Edge Rate
11 = Reserved
Free Running Stoppable
Free Running Stoppable
Free Running Stoppable
Default
0
0
1
10
0
0
0
IDT^TM/ICS^TM Ultra Mobile PC Clock for Automotive use
11
1425A—09/02/09