ICS8S89874I Datasheet, PDF (2/19 Pages) Integrated Device Technology – 1:2 Differential-to-LVPECL Buffer/Divider

ICS8S89874I Data Sheet
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
Q0, nQ0
Output
3, 4
Q1, nQ1
Output
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
5, 15, 16 S2, S1, S0
Input
Pullup Select pins. LVCMOS/LVTTL interface levels.
6
nc
Unused
No connect.
7, 14
8
9
10
11
12
13
V_cc
nRESET
nIN
V_{REF_AC}
V_T
IN
V_EE
Power
Input
Input
Output
Input
Input
Power
Pullup
Positive supply pins.
When LOW, resets the divider. Pulled HIGH when left unconnected. Input threshold
is V_CC/2. Includes a 37kΩ pullup resistor. LVTTL/LVCMOS interface levels.
Inverting differential LVPECL clock input. R_T = 50Ω termination to V_T.
Reference voltage for AC-coupled applications.
Termination input.
Non-inverting LVPECL differential clock input. R_T = 50Ω termination to V_T.
Negative supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
R_PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
kΩ
ICS8S89874BKI REVISION A OCTOBER 22, 2010
2
©2010 Integrated Device Technology, Inc.