ICS8S89874I Datasheet, PDF (1/19 Pages) Integrated Device Technology – 1:2 Differential-to-LVPECL Buffer/Divider

1:2 Differential-to-LVPECL Buffer/Divider
ICS8S89874I
DATA SHEET
General Description
The ICS8S89874I is a high speed 1:2 Differential-to- LVPECL Buffer/
Divider. The ICS8S89874I has a selectable ÷1, ÷2, ÷4, ÷8, ÷16
output divider, which allows the device to be used as either a 1:2
fanout buffer or frequency divider. The clock input has internal
termination resistors, allowing it to interface with several differential
signal types while minimizing the number of required external
components. The device is packaged in a small, 3mm x 3mm
VFQFN package, making it ideal for use on space-constrained
boards.
Features
• Two LVPECL/ECL output pairs
• Frequency divide select options: ÷1 (pass through), ÷2, ÷4, ÷8,
÷16
• IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
• Output frequency: 2GHz (maximum)
• Output skew: 15ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS: 0.20ps (typical)
• LVPECL supply voltage range: 2.375V to 3.63V
• ECL supply voltage range: -3.63V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
S2 ^Pullup
nRESET ^Pullup
Enable
FF
Enable
MUX
0
IN
50Ω
V_T
50Ω
nIN
S0 ^Pullup
S1 ^Pullup
Decoder
V_{REF_AC}
1
00 ÷2
01 ÷4
10 ÷8
11 ÷16
Pin Assignment
16 15 14 13
Q0 1
12 IN
nQ0 2
11 VT
Q1 3
10 VREF_AC
Q0
nQ1 4
9 nIN
56 78
nQ0
Q1
nQ1
ICS8S89874I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89874BKI REVISION A OCTOBER 22, 2010
1
©2010 Integrated Device Technology, Inc.