ICS87001-01 Datasheet, PDF (2/12 Pages) Integrated Device Technology – LVCMOS/LVTTL CLOCK DIVIDER

ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Table 1. Pin Descriptions
Number
Name
Type
Description
1
OE
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
2
V_DD
Power
Power supply pin.
3, 5
CLK0, CLK1
Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
4
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
6, 7, 8
N2, N1, N0
Input Pulldown N divider pins. LVCMOS/LVTTL interface levels. See Table 3.
9, 12
GND
Power
Power supply ground.
10, 11, 13, 15
nc
Unused
No connect.
14
Q
Output
Single-ended clock output. 15Ω output impedance.
LVCMOS/LVTTL interface levels.
16
V_DDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
C_PD
Power Dissipation Capacitance
R_OUT
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
10
15
Maximum
Units
pF
kΩ
kΩ
pF
Ω
Function Tables
Table 3. Programmable Output Divider Function Table
Inputs
N2
N1
N0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
N Divider Value
÷1 (default)
÷2
÷3
÷4
÷5
÷6
÷8
÷16
Output Frequency (MHz)
250
125
83.333
62.5
50
41.667
31.25
15.625
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
2
ICS87001BG-01 REV. A MAY 1, 2009