ICS854S054I Datasheet, PDF (2/14 Pages) Integrated Device Technology – One differential LVDS output pair

ICS854S054I Data Sheet
4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 16
6, 7
9
10
11
12
8, 13
14, 15
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V_DD
SEL0, SEL1
PCLK2
nPCLK2
PCLK3
nPCLK3
GND
nQ, Q
Type
Input
Pulldown
Input
Pullup/
Pulldown
Input
Pulldown
Input
Pullup/
Pulldown
Power
Input
Pulldown
Input
Pulldown
Input
Pullup/
Pulldown
Input
Pulldown
Input
Pullup/
Pulldown
Power
Output
Description
Non-inverting differential clock input.
Inverting differential clock input. V_DD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V_DD/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. V_DD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V_DD/2 default when left floating.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLDOWN
R_VDD/2
Parameter
Input Capacitance
Pulldown Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
75
50
Maximum
Units
pF
kΩ
kΩ
Table 3. Clock Input Function Table
SEL1
0
0
1
1
Inputs
SEL0
0
1
0
1
Outputs
Q
nQ
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
2
©2012 Integrated Device Technology, Inc.