ICS854S054I Datasheet, PDF (1/14 Pages) Integrated Device Technology – One differential LVDS output pair

4:1 Differential-to-LVDS Clock Multiplexer
ICS854S054I
DATA SHEET
General Description
The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer
which can operate up to 2.5GHz. The ICS854S054I has 4 selectable
differential clock inputs. The PCLK, nPCLK input pairs can accept
LVPECL, LVDS or CML levels. The fully differential architecture and
low propagation delay make it ideal for use in clock distribution
circuits. The select pins have internal pulldown resistors. The SEL1
pin is the most significant bit and the binary number applied to the
select pins will select the same numbered data input (i.e., 00 selects
PCLK0, nPCLK0).
Features
• High speed 4:1 differential multiplexer
• One differential LVDS output pair
• Four selectable differential PCLK, nPCLK input pairs
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML
• Maximum output frequency: 2.5GHz
• Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
• Additive phase jitter, RMS: 0.147ps (typical)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 700ps (maximum)
• Supply voltage range: 3.135V to 3.465V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
PCLK0 ^Pulldown
nPCLK0 ^{Pullup/Pulldown}
PCLK1 ^Pulldown
nPCLK1 ^{Pullup/Pulldown}
PCLK2 ^Pulldown
nPCLK2 ^{Pullup/Pulldown}
PCLK3 ^Pulldown
nPCLK3 ^{Pullup/Pulldown}
00 (default)
01
10
11
SEL1 ^Pulldown
SEL0 ^Pulldown
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
Pin Assignment
PCLK0 1
nPCLK0 2
PCLK1 3
nPCLK1 4
V_DD 5
SEL0 6
SEL1 7
GND 8
16 V_DD
15 Q
14 nQ
13 GND
12 nPCLK3
11 PCLK3
10 nPCLK2
9 PCLK2
ICS854S054I
16-Lead TSSOP
Q
5.0mm x 4.4mm x 0.92mm package body
nQ
G Package
Top View
1
©2012 Integrated Device Technology, Inc.