ICS8543BGILF Datasheet, PDF (2/18 Pages) Integrated Device Technology – Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 9, 13
2
3
Name
GND
CLK_EN
CLK_SEL
Type
Power
Input
Pullup
Input
Pulldown
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input. When
LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
4
5
6
7
8
10, 18
11, 12
14, 15
16, 17
19, 20
CLK
nCLK
PCLK
nPCLK
OE
V_DD
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Power
Output
Output
Output
Output
Pulldown
Pullup
Pulldown
Pullup
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
Output enable. Controls enabling and disabling of outputs Q[0:3], nQ[0:3].
LVCMOS/LVTTL interface levels.
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
ICS8543BG REVISION E DECEMBER 17, 2010
2
©2010 Integrated Device Technology, Inc.