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| ICS8543BGILF Datasheet, PDF (12/18 Pages) Integrated Device Technology – Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer | |||
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ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
3.3V LVPECL Clock Input Interface
The PCLK/nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 4A to 4E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
CML
Zo = 50â¦
Zo = 50â¦
3.3V
R1
R2
50â¦
50â¦
3.3V
PCLK
nPCLK
LVPECL
Input
3.3V
CML Built-In Pullup
Zo = 50â¦
Zo = 50â¦
3.3V
R1
100â¦
PCLK
nPCLK
LVPECL
Input
Figure 4A. PCLK/nPCLK Input Driven by a CML Driver
Figure 4B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
LVPECL
Zo = 50â¦
Zo = 50â¦
3.3V
R3
125â¦
R4
125â¦
3.3V
PCLK
nPCLK
LVPECL
R1
R2
84â¦
84â¦
Input
Figure 4C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
2.5V
SSTL
Zo = 60â¦
Zo = 60â¦
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
LVPECL
Input
3.3V
3.3V LVPECL
Zo = 50â¦
Zo = 50â¦
R5
R6
100⦠- 200⦠100⦠- 200â¦
3.3V
C1
PCLK
C2
VBB
nPCLK
LVPECL
R1
R2
50⦠50â¦
Input
Figure 4D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
Figure 4E. PCLK/nPCLK Input Driven by a
2.5V SSTL Driver
ICS8543BG REVISION E DECEMBER 17, 2010
12
©2010 Integrated Device Technology, Inc.
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