ICS844004-104 Datasheet, PDF (2/16 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

ICS844004-104
FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 2
3
4
5, 6, 7, 8, 15,
16, 20, 21,
28, 29
9
10,
12
11
13,
14
17, 22
18
19
23, 24
25, 32
26, 27
30, 31
Name
Q0, nQ0
MR
nPLL_SEL
nc
V_DDA
F_SEL0,
F_SEL1
V_DD
XTAL_OUT
XTAL_IN
GND
REF_CLK
nXTAL_SEL
nQ3, Q3
V_DDO
Q2, nQ2
nQ1, Q1
Type
Output
Input Pulldown
Input Pulldown
Unused
Power
Input
Power
Input
Power
Input
Pulldown
Pulldown
Input Pulldown
Output
Power
Output
Output
Description
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When LOW,
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Frequency select pin. LVCMOS/LVTTL interface levels.
Core supply pin.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Power supply ground.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects between crystal or REF_CLK inputs as the PLL Reference source.
Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
2
ICS844004AK-104 REV. A SEPTEMBER 15, 2008