ICS844004-104 Datasheet, PDF (14/16 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

ICS844004-104
FEMTOCLOCK™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Reliability Information
Table 8. θ_JA vs. Air Flow Table for a 32 Lead VFQFN
θ_JA vs. Air Flow
Meter per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
42.4°C/W
Transistor Count
The transistor count for ICS844004-104 is: 2914
1
37.0°C/W
2.5
33.2°C/W
Package Outline and Package Dimensions
Package Outline - K Suffix for VFQFN Packages
Ind exArea
N
To p View
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
S eating Plan e
A1
Anvil
Singula tion
OR
A3 ^L
E 2 _E2
2
(N -1)x e
(R ef.)
(Ref.)
N &N
Even
N
e (Ty p.)
2 _{If N & N}
1 ^{are Even}
2
(N -1)x e
(Re f.)
A
0. 08 C
e
(Ref.)
N &N
Odd
C
D2
2
D2
b
Th er mal
Ba se
Table 9. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
N_D & N_E
D&E
8
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This
drawing is not intended to convey the actual pin count or pin layout
of this device. The pin count and pinout are shown on the front
page. The package dimensions are in Table 8 below.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
14
ICS844004AK-104 REV. A SEPTEMBER 15, 2008