ICS83940DI Datasheet, PDF (2/19 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER

ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
1, 2, 12, 17, 25
GND
3
LVCMOS_CLK
4
CLK_SEL
5
6
7, 21
8, 16, 29
9, 10, 11,
13, 14, 15,
18, 19, 20,
22, 23, 24,
26, 27, 28,
30, 31, 32
PCLK
nPCLK
V_DD
V_DDO
Q17, Q16, Q15,
Q14, Q13, Q12,
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
Type
Power
Input
Pulldown
Input
Pulldown
Input
Input
Power
Power
Pulldown
Pullup/
Pulldown
Description
Power supply ground.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects PCLK, nPCLK inputs.
LVCMOS / LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V_DD/2 default when left floating.
Power supply pin.
Output supply pins.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
R_PULLUP
R_PULLDOWN
C_PD
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
R_OUT
Output Impedance
Test Conditions
Minimum
18
Typical
4
51
51
6
Maximum
28
Units
pF
k
k
pF

ICS83940DYI REVISION C MARCH 20, 2013
2
©2013 Integrated Device Technology, Inc.