ICS83940DI Datasheet, PDF(13/19 Page) Integrated Circuit Systems – LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

ICS83940DI Datasheet, PDF (13/19 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER

◁

ICS83940DI Data Sheet

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 3. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as âheat

pipesâ. The number of vias (i.e. âheat pipesâ) are application specific

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, please refer to the Application

Note on the Surface Mount Assembly of Amkorâs Thermally/

Electrically Enhance Leadframe Base Package, Amkor Technology.

SOLDER

EXPOSED HEAT SLUG

SOLDER

PIN PAD

GROUND PLANE

THERMAL VIA

LAND PATTERN

(GROUND PAD)

PIN PAD

Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path â Side View (drawing not to scale)

Recommendations for Unused Input and Output Pins

Inputs:

PCLK/nPCLK Inputs

For applications not requiring the use of the differential input, both

PCLK and nPCLK can be left floating. Though not required, but for

additional protection, a 1kï resistor can be tied from PCLK to

ground.

LVCMOS_CLK Input

For applications not requiring the use of a clock input, it can be left

floating. Though not required, but for additional protection, a 1kï

resistor can be tied from the LVCMOS_CLK input to ground.

LVCMOS Control Pins

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1kï resistor can be used.

Outputs:

LVCMOS Outputs

All unused LVCMOS output can be left floating. There should be no

trace attached.

ICS83940DYI REVISION C MARCH 20, 2013

▷