ICS621 Datasheet, PDF (2/10 Pages) Integrated Device Technology – LOW SKEW 1 TO 4 CLOCK BUFFER

ICS621
LOW SKEW 1 TO 4 CLOCK BUFFER
Pin Assignment (8-pin SOIC)
ICLK
1
Q1
2
Q2
3
Q3
4
8
OE
7
VDD
6
GND
5
Q4
FAN OUT BUFFER
Pin Assignment (8-pin DFN)
ICLK ¹
Q1
Q2
Q3 ⁴
8 OE
VDD
GND
5 Q4
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
Q1
Q2
Q3
Q4
GND
VDD
OE
Pin
Type
Input
Output
Output
Output
Output
Power
Power
Input
Pin Description
Clock Input. 3.3 V tolerant input.
Clock Output 1.
Clock Output 2.
Clock Output 3.
Clock Output 4.
Connect to ground.
Connect to +1.2 V or +1.8 V.
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF
should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 Ω series
terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the ICS621 is capable of, careful attention must be paid to board layout.
Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they
do not, the output skew will be degraded. For example, using a 30Ω series termination on one output (with 33Ω on
the others) will cause at least 15 ps of skew.
IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER
2
ICS621
REV B 030907