9EX21501A Datasheet, PDF (2/15 Pages) Integrated Device Technology – 15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux

9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
PIn Configuration
Datasheet
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
OE9# 1
48 DIF_6#
DIF_9 2
47 DIF_6
DIF_9# 3
46 OE6#
OE10# 4
45 DIF_5#
DIF_10 5
44 DIF_5
DIF_10# 6
43 OE5#
OE11# 7
42 DIF_4#
DIF_11 8
DIF_11# 9
9EX21501
41 DIF_4
40 DIF_3#
GND 10
39 DIF_3
VDD 11
38 GND
DIF_12 12
37 VDD
DIF_12# 13
36 DIF_2#
OE12# 14
35 DIF_2
DIF_13 15
34 DIF_1#
DIF_13# 16
33 DIF_1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-pin MLF
Frequency/Functionality Table
Byte 0,
bit 2
Byte 0,
Byte 0,
(100_133M#
bit 1
bit 0
Latch)
FSB
FSA
1
0
1
0
0
1
0
1
1
0
1
0
0
0
0
1
0
0
1
1
0
1
1
1
Input
MHz
100.00
133.33
166.67
200.00
266.67
333.33
400.00
DIF_x
MHz
100.00
133.33
166.67
200.00
266.67
333.33
400.00
Reserved
Notes
1
1
2
2
2
2
2
Notes:100M_133M#
1. Latch selects between 100 and 133 MHz.
This is equivalent to FSC in CK410B+/CK509B FS table.
2. Writing Byte 2 bits (2:0) can select other frequencies.
These frequencies are not characterized in PLL Mode
HIBW_BYPM_LOBW# Selection (Pin 54)
State
Voltage
Mode
Low
<0.8V
Low BW
Mid
1.2<Vin<1.8V Bypass
High
Vin > 2.0V High BW
Power Groups
Pin Number
VDD
GND
23
22
29
26
11,17,37,49, 64 10, 38
Description
Main PLL, Analog
Input buffers
DIF clocks
Power Down Functionality
INPUTS
CKPWRGD/PD#
Input
1
Running
0
X
OUTPUTS
DIF_x
Running
Hi-Z
SMBus Address Selection (pins 57, 58)
SMB_A1
SMB_A0 Address
0
0
D4
0
1
D6
1
0
D8
1
1
DA
PLL State
ON
OFF
IDT^® 15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
2
1578—01/18/11