9EX21501A Datasheet, PDF (10/15 Pages) Integrated Device Technology – 15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux

9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
Datasheet
General SMBus serial interface information for the 9EX21501
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4 _(H)
• ICS clock will acknowledge
• Controller (host) sends the beginning byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D4 _(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D5 _(H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X_(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controlle r (Host)
T
starT bit
ICS (Sla ve /Re ce ive r)
S lave Address D4_(H)
WR
W Rite
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P
stoP bit
ACK
Note: SMBus address is selectable among 4 addresses.
See tabel on page 2.
IDT^® 15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
10
Index Block Read Operation
Controlle r (Host)
T
starT bit
ICS (Sla ve /Re ce ive r)
S lave Address D4_(H)
WR
W Rite
ACK
Beginning Byte = N
ACK
RT
Repeat starT
S lave Address D5_(H)
RD
ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N
Not acknowledge
P
stoP bit
Byte N + X - 1
1578—01/18/11