8S89296 Datasheet, PDF (2/16 Pages) Integrated Device Technology – LVDS Programmable Delay Line

Pin Assignments
Figure 2: Pin Assignments for 5mm x 5mm 32-Lead Package
32 31 30 29 28 27 26 25
D8 1
24 GND
D9 2
23 D0
D10 3
IN 4
nIN 5
8S89296
22 V_DD
21 Q
20 nQ
V_BB 6
V_EF 7
19 VDD
18 V_DD
V_CF 8
17 FTUNE
9 10 11 12 13 14 15 16
8S89296 Datasheet
Pin Description and Pin Characteristic Tables
Table 1: Pin Descriptions
Number
1
Name
D8
2
D9
3
D10
4
IN
5
nIN
6
V_BB
7
V_EF
8
V_CF
9
GND
10
LEN
Type^[a]
Input (PD)
Input (PD)
Input (PD)
Input (PD)
Input (PU/ PD)
Output
Output
Input
Power
Input (PD)
Description
Parallel data input D8.
Single-ended LVCMOS, LVTTL, LVPECL interface levels.
Parallel data input D9.
Single-ended LVCMOS, LVTTL, LVPECL interface levels.
Parallel data input D10.
Single-ended LVCMOS, LVTTL, LVPECL interface levels.
Non-inverting differential input.
Inverting differential input.
Reference voltage output. This pin can be used to re-bias AC-coupled inputs to IN
and nIN. When used, de-couple to V_DD using a 0.01F capacitor. If not used, leave
floating.
Reference voltage output. See Table 4.
Reference voltage input. The voltage driven on V_CF sets the logic transition
threshold for D[10:0].
Power supply ground.
D inputs LOAD and HOLD control input. When HIGH, latches the D[10:0] bits. When
LOW, the D[10:0] latches are transparent. Single-ended LVPECL interface levels.
See Table 3.
©2017 Integrated Device Technology, Inc.
2
February 14, 2017