8S89296 Datasheet, PDF (1/16 Pages) Integrated Device Technology – LVDS Programmable Delay Line

LVDS Programmable Delay Line
8S89296
Datasheet
Description
The 8S89296 is a high performance LVDS programmable delay line.
The delay can vary from 2.2ns to 12.5ns in 10ps steps. The 8S89296
is characterized to operate from a 2.5V power supply and is
guaranteed over industrial temperature range.
The delay of the device varies in discrete steps based on a control
word. A 10-bit long control word sets the delay in 10ps increments.
Also, the input pins IN and nIN default to an equivalent low state
when left floating. The control register can accept CMOS or TTL
level signals.
Block Diagram
Figure 1: Block Diagram
Features
▪ One LVDS level output
▪ One differential clock input pair
▪ Differential input clock (IN, nIN) can accept the following signaling
levels: LVPECL, LVDS, CML
▪ Maximum frequency: 800MHz
▪ Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps
▪ D[10:0] can accept LVPECL, LVCMOS or LVTTL levels
▪ Full 2.5V supply voltages
▪ -40°C to 85°C ambient operating temperature
▪ Available in lead-free (RoHS 6) package
IN
nIN
nEN
0
1
512
GD
0
1
256
GD
0
1
128
GD
0
1
64
GD
0
1
32
GD
GD = Gate Delay
0
1
16
GD
0
1
8
GD
0
1
4
GD
0
1
2
GD
0
1
1
GD
FTUNE
D[9:0]
LEN
SETMIN
SETMAX
10-bit
Latch
0
Q
1
1
nQ
GD
D[10]
LEN
VBB
VCF
VEF
Latch
©2017 Integrated Device Technology, Inc.
1
CASCADE
nCASCADE
Transistor count: 8686
February 14, 2017