8S89296 Datasheet, PDF (10/16 Pages) Integrated Device Technology – LVDS Programmable Delay Line

8S89296 Datasheet
2.5V LVPECL Clock Input Interface
The IN/nIN accepts LVPECL, LVDS, CML and other differential signals. Both differential signals must meet the V_PP and V_CMR input
requirements. Figure 5 to Figure 9 show interface examples for the IN/nIN input driven by the most common driver types. The input interfaces
suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor
of the driver component to confirm the driver termination requirements.
Figure 5. IN/nIN Input Driven by a CML Driver
2.5V
CML
Zo = 50Ω
Zo = 50Ω
2.5V
R1
R2
50
50
2.5V
IN
nIN
LVPECL
Differential
Inputs
Figure 6. ON/nIN Input Driven by a
2.5V LVPECL Driver
2.5V
2.5V
Zo = 50Ω
R3
R4
125
125
LVPECL
Zo = 50Ω
R1
R2
84
84
2.5V
IN
nIN
LVPECL
Differential
Inputs
Figure 7. IN/nIN Input Driven by a 2.5V LVDS Driver Figure 8. IN/nIN Input Driven by a
Built-In Pullup CML Driver
2.5V
Zo = 50Ω
LVDS
R5
100
Zo = 50Ω
2.5V
C1
C2
R1
R2
1k
1k
IN
VBB
nIN
LVPECL
Differential
Inputs
C3
0.1µF
2.5V
CML Built-In Pullup
Zo = 50Ω
Zo = 50Ω
2.5V
IN
R1
100
nIN
LVPECL
Differential
Inputs
Figure 9. IN/nIN Input Driven by a
2.5V LVPECL Driver with AC Couple
2.5V
2.5V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
100 - 200
R6
100 - 200
C1
C2
R1
R2
50
50
2.5V
IN
VBB
nIN _LVPECL
Differential
Inputs
©2017 Integrated Device Technology, Inc.
10
February 14, 2017