83940D Datasheet, PDF (2/16 Pages) Integrated Device Technology – Maximum output frequency

83940D DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 12, 17, 25
GND
Power
Power supply ground.
3
4
5
6
7, 21
8, 16, 29
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V_DD
V_DDO
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Input
Input
Input
Input
Power
Power
Output
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
Pulldown input when HIGH. Selects PCLK, nPCLK inputs when
LOW. LVCMOS / LVTTL interface levels.
Pulldown Non-inverting differential LVPECL clock input.
Pullup/ Inverting differential LVPECL clock input.
Pulldown V_DD/2 default when left floating.
Core supply pins.
Output supply pins.
Clock outputs. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
C_PD
R_PULLup
R_PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Test Conditions
Minimum Typical Maximum Units
4
pF
6
pF
51
KΩ
51
KΩ
18
28
Ω
Control Input
CLK_SEL
0
1
PCLK, nPCLK
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLK_SEL LVCMOS_CLK
PCLK
nPCLK
Outputs
Q0:Q17
Input to Output Mode
Polarity
0
—
0
1
LOW
Differential to Single Ended Non Inverting
0
—
1
0
HIGH
Differential to Single Ended Non Inverting
0
—
0
Biased;
NOTE 1
LOW
Single Ended to Single Ended Non Inverting
0
—
1
Biased;
NOTE 1
HIGH
Single Ended to Single Ended Non Inverting
0
—
Biased; NOTE 1
0
HIGH
Single Ended to Single Ended Inverting
0
—
Biased; NOTE 1
1
LOW
Single Ended to Single Ended Inverting
1
0
—
—
LOW
Single Ended to Single Ended Non Inverting
1
1
—
—
HIGH
Single Ended to Single Ended Non Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
LOW SKEW, 1-TO-18
2
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
REVISION B 3/25/15