8343-01 Datasheet, PDF (2/13 Pages) Integrated Device Technology – Maximumoutputfrequency

8343-01 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions¹
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Name
V_DD1
V_DD1
V_DD1
Q3
Q4
GND
GND
GND
Q5
Q6
Q7
CLK
V_DD
Q8
Q9
Q10
GND
GND
GND
Q11
Q12
V_DD2
V_DD2
V_DD2
Q13
Q14
Q15
Type
Power
Power
Power
Output
Output
Power
Power
Power
Output
Output
Output
Input
Pulldown
Power
Output
Output
Output
Power
Power
Power
Output
Output
Power
Power
Power
Output
Output
Output
Description
Q0 through Q7 output supply pin.
Q0 through Q7 output supply pin.
Q0 through Q7 output supply pin.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
Power supply ground.
Power supply ground.
Power supply ground.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock input / 5V tolerant.
Core supply pin.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
Power supply ground.
Power supply ground.
Power supply ground.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
Q8 through Q15 output supply pin.
Q8 through Q15 output supply pin.
Q8 through Q15 output supply pin.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
28
OE2
Input
Pullup
Output enable. When low forces outputs Q8 through Q15 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
29
OE1
Input
Pullup
Output enable. When low forces outputs Q0 through Q7 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
30
Q0
Output
LVCMOS/LVTTL clock output. 7typical output impedance.
31
Q1
Output
LVCMOS/LVTTL clock output. 7typical output impedance.
32
Q2
Output
LVCMOS/LVTTL clock output. 7typical output impedance.
NOTE 1: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
2
REVISION B 08/25/14