74FCT38072S Datasheet, PDF (2/11 Pages) Integrated Device Technology – Low additive phase jitter RMS

74FCT38072S DATASHEET
Pin Assignments
VDD 1
VDD 2
ICLK 3
GND 4
8 GND
7 Q1
6 Q0
5 GND
8-pin SOIC
VDD 1
VDD 2
ICLK 3
GND 4
8 GND
7 Q1
6 Q0
5 GND
8-pin DFN
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
VDD
VDD
ICLK
GND
GND
Q0
Q1
GND
Pin
Type
Power
Power
Input
Power
Power
Output
Output
Power
Pin Description
Connect to +1.8V, +2.5 V, or +3.3 V.
Connect to +1.8V, +2.5 V, or +3.3 V.
Clock input.
Connect to ground.
Connect to ground.
Clock output 0.
Clock output 1.
Connect to ground.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF should be
connected between VDD pin and GND pin, as close to the device as possible. A 33  series terminating resistor may be used
on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the 74FCT38072S is capable of, careful attention must be paid to board layout. Essentially,
both outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will
be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15 ps of
skew.
LOW SKEW 1 TO 2 CLOCK BUFFER
2
REVISION A 03/18/15